1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices, and more specifically, to a method of fabricating a multiple-layer, interconnected substrate for use in the manufacture of single or multiple chip packages.
2. Description of the Prior Art
Multiple-layer, interconnected substrates are used in the manufacture of multi-chip modules (MCM) and single-chip modules (SCM), and in chip-scale packaging (CSP). The interconnected substrates may be rigid or flexible and are used to provide signal paths, power distribution paths, and interconnections between locations on the substrates. Use of multiple layers facilitates an increase in the density of integrated circuits (ICs) which can be mounted on the top substrate because it permits signal and power lines to be placed on layers other than that on which the ICs are mounted.
The use of multiple substrate layers requires that a method be developed for interconnecting the substrates to enable signals and power to be routed between the pins of different ICs and between the IC pins and connections on the package. One way in which this is conventionally achieved is by forming a through hole that extends through vertically aligned regions on different substrate layers. The through hole is typically formed by a mechanical or laser drill, or plasma etching, for example, with the hole being plated to provide a conductive interconnection between the layers.
However, there are several disadvantages to this conventional method. The method is limited with regards to the substrate and conductive materials with which it may be used. Also, it is a single-sided process and is not suitable for forming double-sided connections (i.e., conductive connections to an intermediate layer from above and below that layer). In addition, this method does not permit selective interconnection to only those layers requiring it, since the through hole extends through all of the layers.
Another conventional method for forming a multi-layer interconnected substrate is to pattern the via hole(s) in each of the individual layers and fill the via hole(s) with a conductive material prior to assembling them into the final structure. This method has the disadvantage that all of the layers must be carefully aligned prior to laminating them together. This means that the feature routing density achievable is limited by the need to provide for sufficient registration tolerance between the layers of the structure. In addition, this method requires a greater number of processing steps than may be feasible or efficient for process flows in which it is desired to be incorporated.
What is desired is a method of fabricating a multi-layer interconnected substrate having a higher feature routing density than can be achieved with conventional process flows.